This invention relates to insulated gate field effect transistors (IGFET) and more particularly to such a transistor exhibiting a small PN junction capacitance between the substrate of one type conductivity and the source and/or drain of the other conductivity type.
In general, the limitations on operating speed of IGFETs are imposed mainly by device gain and capacitances including those of the PN junctions of the device itself that are in the load circuit.
Since the highly conductive source and drain regions have a much higher dopant concentration than does the substrate, junction capacitance of source and drain can be reduced by using a higher resistivity substrate. However, the minimum practical impurity concentration in the substrate of an integrated circuit is that for which the junction depletion width is not the limiting factor to packing density.
A known solution to this problem is to implant impurities of opposite conductivity to that of the substrate to the specific depth of the source/drain-substrate junctions to create a thin intrinsic region just under the source and drain. However, this process entails a subsequent annealing step that further drives all previously incorporated impurities. That annealing is preferably avoided as being additionally complicating and degrading of integrated circuit performance.
A widely used approach for making IGFET's includes a blanket ion implantation of impurities through an oxide layer into an entire device area to adjust the threshold of the IGFET device. Then a blanket polysilicon layer is deposited, a photoresist mask is formed thereover and through the mask the polysilicon is etched away leaving only a polysilicon gate. Source and drain regions are then formed using the gate as a mask. An example of such a self-aligned gate method is found in the patent to Owens et al, U.S. Pat. No. 4,598,460 issued July 8, 1986 and assigned to the same assignee as is the present invention. However, if high concentration channel doping is included throughout the device area, the junction capacitances of source and drain increases as a direct result of that blanket channel-adjust and device speed is thereby diminished.
To overcome this problem it has been proposed that the channel-adjust implantation be accomplished selectively at the gate area only through both the oxide layer and an overlying thin layer of polysilicon. The polysilicon is sputter deposited. It is impossible to use the more efficient chemical vapor deposition method because it must be executed at temperatures no lower than about 400.degree. C. which would destroy the underlying photoresist. Then using the same mask a high-melting-metal and silicon are cosputtered. The mask and unwanted metal are removed by a lift off process and the metal and silicon are sintered at about 900.degree. C. to form a compound self-aligned gate consisting of a first layer of polysilicon and a second layer of metal silicide.
This process retains the advantage of self-aligned gates but is complex, expensive and critical to control due at least to the use of the critical mask lift off steps, the metal silicde deposition steps, and the high temperature anneal step. The lift off process is particularly critical because if, at any point in an aperture of the photoresist mask the photoresist wall is not almost absolutely vertical, the silicide at that point will not be discontinuous and the mask will not lift off.
It is therefore an object of this invention to overcome the shortcomings in the prior art and to provide a relatively simple and reliable method for making a FET having a small PN junction capacitance between the substrate and the source and/or drain.